The invention relates generally to thin film devices having a functional metal oxide layer, for example, a perovskite ferroelectric memory or high dielectric constant capacitor material. In particular, the invention relates to forming such thin film devices on silicon substrates.
Significant advancements have been accomplished in the past few years in the growth and processing of ferroelectric and high dielectric metal oxide thin films for a variety of microelectronic applications. Much of the work has focused on potential integration of these metal oxide films into volatile and non-volatile memories although other applications are also being explored. These efforts blossomed in the early 1980s primarily through pioneering efforts in the sol-gel processing, chemical vapor deposition (CVD), and sputter deposition of multi-component metal oxide thin films. These techniques facilitated the fabrication of sub-micron thin films of ferroelectric materials such as lead zirconate titanate (PZT) and other cationically substituted derivatives of PZT on silicon substrates. Applications other than memories include cuprate thin films for superconducting junctions and microwave devices and magnetic perovskites for magneto transport devices.
The prototypical structure for a high-density non-volatile memory cell that has evolved from these efforts is schematically illustrated in FIG. 1, but other structures are available. A large number of memory cells, one of which is illustrated, are formed in a silicon substrate 10. Ion implantation is used to dope a source 12 and drain 14 into the substrate 10. A pass gate transistor structure including a gate oxide 16 and metallization 18 is formed over the gate region between the source 12 and drain 14 to produce a MOS transistor. Electrical power or sensing circuitry is selectively connected to the source 12 by an unillustrated line and is gated by the signal applied to the gate structure through the metallization 18. The transistor structure is then covered with a first-level dielectric layer 20 typically of SiO2 or a related silicate glass. A contact hole is etched in the oxide dielectric layer 20 over the transistor drain. Polycrystalline silicon is filled into the contact hole to form a silicon plug 22 making electric contact with the transistor drain 14.
The ferroelectric device, in this case, a ferroelectric memory capacitor, is formed over the polysilicon plug 22. The vertically oriented capacitor is electrically contacted at its bottom through the polysilicon plug 22 and silicon drain 14 of the transistor structure and at its more exposed top by a second signal line. The dramatic difference in chemistries between the ferroelectric oxides and the underlying silicon necessitates the introduction of a diffusion barrier to eliminate any diffusion of oxygen from the metal oxide ferroelectric layer or other oxide layers to the components of the semiconductor transistor. Even the oxidation of the top of the silicon plug 22 would create a insulative electrical barrier of SiO2 between the ferroelectric capacitor cell and the silicon transistor. The fact that the barrier must be a good electrical conductor and form an ohmic contact to silicon further complicates the selection of barrier materials.
For reasons to be discussed immediately below, a typical barrier consists of a layer 24 of titanium nitride (TiN) and a layer 26 of platinum immediately underlying a lower electrode layer 28. These layers 24, 26, 28 are patterned to form a lower ferroelectric stack. A shaped diffusion barrier layer 30, for example, of titanium oxide (TiO2) is deposited and patterned to have an aperture over the top of the lower ferroelectric stack. A ferroelectric layer 32 is then deposited, for example of PZT or its generalization of lead lanthanum niobate zirconate titanate (PLNZT), followed by an upper electrode layer 34, and an upper platinum barrier layer 36. The TiO2 diffusion barrier layer 30, the ferroelectric layer 32, the upper electrode layer 36, and the upper platinum barrier layer 34 are patterned to have larger area than that of the aperture over the lower ferroelectric stack. These depositions complete the ferroelectric stack.
An SiO2 inter-level dielectric layer 38 is deposited and patterned to have a via hole overlying the upper platinum electrode layer 36 of the ferroelectric stack. A contact barrier layer 40, for example of conductive TiN or TiW, is coated at the bottom of the via hole, and a metallization 42, for example, of aluminum or tungsten, is filled into the remainder of the via hole, thereby providing an upper electrical contact to the ferroelectric stack.
Platinum is chosen for the barrier, particularly the lower barrier, primarily because of its refractory nature and resistance to oxidation, unlike, for example, the more commonly used conductor aluminum. Platinum barriers enable ferroelectric capacitors with very desirable basic properties, such as large values of remanent polarization AP, ferroelectric film resistivities of greater than 1010 xcexa9-cm, and sufficient retention characteristics.
Titanium nitride is another obvious choice for a barrier layer, especially since it is already widely used in the semiconductor industry as a diffusion barrier. Unfortunately, TiN oxidizes at about 500xc2x0 C., which is much lower than the optimum process temperature for ferroelectric materials. To overcome the shortcoming of the TiN in terms of temperature, platinum and iridium (Ir) have been used as materials for protective layers. Another common approach is to dope TiN with Al to form (Ti, Al)N or to use silicides or other complex structures. The most common approaches being currently explored use a combination of at least two layers to create a composite barrier layer, such as that in FIG. 1. Taking the PZT ferroelectric material as an example, one approach uses the combination of (Ti, Al)N/(Pt, Ir) as the composite barrier. The structure of FIG. 1 uses a special case of this composite barrier.
However, the above structure presents continuing problems. Even though platinum is a refractory metal and does not oxidize, it is nonetheless fairly porous to oxygen. That is, it does not prevent oxygen from diffusing to the underlying silicon plug and oxidizing a resistive surface layer there. Furthermore, such devices have been observed to suffer fundamental reliability problems. For example, if the test capacitors are repeatedly cycled for more than 107 to 108 bipolar cycles, the amount of remanent polarization still available becomes progressively smaller, and eventually the non-volatile capacitor functionally fails.
The use of platinum or iridium in the barrier or other parts of the stack structure presents other technological and strategic problems. First, dry etching of Pt or Ir is still very difficult although there have been some recent breakthroughs. A dry etch process, such as reactive ion plasma etching, is considered to be essential for commercial memories to be manufacturable with high yield. Since both Pt and Ir are relatively inert (although Ir does form stable oxides), the ability to form volatile reaction species during dry etching appears to be severely limited. Secondly, both Pt and Ir are considered to be precious metals, not only expensive but also of uncertain supply in such quantities required for widespread commercialization. As a result, the economics of supply and demand may impact the feasibility and dependability of using these precious metals in large quantities.
In view of the problems with platinum and iridium, one of the present inventors, Ramesh, and others have developed the use of other alloys and compounds that eliminate the need for including these precious metals. The results have been scientifically interesting and offer much promise. Dhote et al. in U.S. Pat. No. 5,777,356 describe the use of intermetallic alloys as the conducting barrier layer, without the use of Pt or Ir. An intermetallic alloy is typically composed of two refractory metals in relative compositions that are stoichiometric or nearly so. This approach has been shown to be effective with a Ti/Al-based intermetallic alloy directly contacting the polysilicon plug. A metal oxide, lanthanum strontium cobaltate (LSCO) is used as the lower electrode since it has been observed to provide some crystallographic templating for the overgrown PZT ferroelectric. However, the templating is effective only for the out-of-plane orientation, and the in-plane orientation is polycrystalline in a pattern which may be characterized as a mosaic crystal or (001) fiber-textured material.
Ramesh has also suggested another approach in U.S. Pat. No. 5,270,298 in which a barrier layer of ytrria-stabilized zirconia (YSZ) is overlaid by a strongly templating layer of an anisotropic perovskite such as bismuth titanate before the LSCO electrode is deposited. The templating layer controls the crystallographic orientation and assures the phase stability of the over grown cubic LSCO perovskite layer. This approach has proven very effective, but it requires the deposition of two different layers, namely the buffer and templating layers.
Non-volatile memories relying upon ferroelectric capacitors are generally used in a mode requiring traversing the hysteretic loop during every read or write operation, hence their designation of destructive read-out memories (DROs). A resulting problem, termed fatigue, often limits the operation of non-volatile ferroelectric memories to a large but limited number of read/write cycles, after which the hysteric loop turns more resistive with reduced separation between the two memory states. The problem of fatigue has in large part been overcome through either of two approaches, either using conductive metal oxide electrodes which templates the overlying material into a crystalline phase or replacing the PZT with another ferroelectric material, strontium bismuth titanate (SBT). However, the templating provided by conductive metal oxides such as LSCO is incomplete, and the resulting PZT is only (001)-textured. This can be overcome by use of additional layers, such as YSZ or bismuth strontium titanate (BST), but the number of required deposition steps is increased, and the monocrystallinity of the PZT is still not guaranteed. On the other hand, SBT is disadvantageous.
Ramesh et al. have recently disclosed a different approach for a related structure in U.S. Pat. No. 6,432,546, incorporated herein by reference in its entirety. In this process, a layer of (Ba, Sr)TiO3 is grown on a crystalline silicon wafer. The preferred composition is strontium titanate (SrTiO3 or simply STO), which is grown under conditions that the strontium titanate is grown to be epitaxial to the silicon, that is, monocrystalline, and the subsequently deposited LSCO and PZT are also monocrystalline. FIG. 2 shows a hysteresis curve 50 for polycrystalline PZT, hysteresis curve 52 for (001)-textured PZT, and hysteresis curve 54 for epitaxial and monocrystalline PZT grown on strontium titanate that is epitaxially grown on monocrystalline silicon according to the method of the afore cited patent application to Ramesh et al. Clearly, epitaxial PZT shows the best behavior with both the saturation and remanent polarization increasing with crystallinity. X-ray diffraction data verify the crystalline states of the samples, as described above.
However, strontium titanate cannot be simply added to the memory cell structure of FIG. 1 since strontium titanate is a dielectric or at best a semiconductor, having a room temperature resistivity of somewhat more than 1 xcexa9-cm, which for a 100 nm or even 1 xcexcm square conduction path amounts to a small strontium titanate capacitor in series with a large PZT capacitor so that a substantial part of the entire voltage drop is across the parasitic STO capacitor. As a result, the use of an STO barrier requires providing another current path into the lower capacitor electrode than through the underlying silicon. The memory cell structure illustrated in the afore cited patent application to Ramesh et al. includes a separate top contact to the bottom LSCO electrode providing a conductive path that avoids the STO layer.
It would be greatly desired to provide a barrier layer over silicon that is epitaxial to silicon and is also electrically conductive.
It would be also desired to extend the concepts of templating STO layers to other classes of devices and to improve upon the known types of STO templating.
According to an underlying aspect of the invention, a conductive barrier layer is formed between a silicon substrate, preferably a crystalline one, and a perovskite functional layer, such as part of a ferroelectric device. The conductive barrier layer may be composed of various materials, the most intensively studied of which are those composed of doped strontium titanate. The doping may be effected by substitution of one of the cations, whether of the larger strontium cation by, for example, lanthanum or of the smaller titanium cation by, for example, niobium, tantalum, or tungsten or possibly molybdenum or rhenium. Other doping constituents are possible. Instead of lanthanum, a dopant of another member of the lanthanide series, bismuth, antimony, or yttrium may be used. Alternatively, the strontium titanate may be deficient in oxygen, that is, anionically deficient. Other conductive barrier materials are available, for example, of the structural perovskite ABO3 or of the perovskite-related structural families of the Ruddlesen-Popper phases An+1BnO3n+1. A preferred maximum resistivity is 0.01 xcexa9-cm.
According to one aspect of the invention, the large strontium cation is substituted by lanthanum to form a conductive barrier layer of (La, Sr)TiO3 between a silicon under layer and a functional metal oxide layer, such as a ferroelectric device. Preferably, the silicon underplayed is monocrystalline and the barrier layer acts as a template so that the functional metal oxide layer and any intermediate metal oxide electrode layers form epitaxially to the silicon underplayed. Yttrium and metal of the lanthanide group may also be substituted.
According to a second aspect of the invention, the small titanium cation is substituted by niobium, tantalum, or tungsten to form a conductive barrier layer of, for example, (Sr, Ba)(Ti, Nb, Ta, W)O3 between a silicon underplayed and a functional metal oxide layer. Other metals may also be substituted.
According to a third aspect of the invention, strontium titanate or similar metal oxide is made deficient in oxygen to form a conductive barrier layer.
Any of the above three aspects of the invention may be combined.
Strontium ruthenate (SrRuO3) and some other cubic perovskite are other materials to form a conductive barrier and template layer.
According to fourth aspect of the invention, a barrier layer of (Sr, Ba) (Ti, Nb, Ta, W)O3 or (La, Sr)TiO3, or a combination thereof, which is not necessarily conductive and may include SrTiO3 is used as a templating barrier for the growth of monocrystalline functional metal oxide films used for both non-volatile ferroelectric memories and for other applications.
According a fifth aspect of the invention, the composition of the (La, Ca, Sr, Ba) (Ti, Nb, Ta, W)O3 film is chosen to be lattice matched to silicon. Other related compositions may also be used.
According to a sixth aspect of the invention, an epitaxial metallic layer is grown between the silicon underplayed and the conductive barrier layer and may include either an intermetallic alloy or a silicide or a silicide and matching metal oxide.
The invention is particularly useful in which the conductive barrier electrically connects the underlying silicon to an electrode layer, the functional metal oxide layer is formed over the electrode layer and both the electrode layer and the functional oxide layer are epitaxial to the underlying silicon. A commercially important use is for a ferroelectric element, such as a memory cell in which the function oxide layer is a ferroelectric material and is overlaid with a second electrode layer.